Xilinx Courses
ISE Design Tool Flow
Duration: 1 Day
Course Date: 28 Mac | 11 May | 30 Jun | 18 Jul | 15 Aug | 18 Nov
ISE Design Tool Flow provides the overall context and framework for the development cycle of FPGAs. For those uninitiated to FPGA design, this course will arm you with the proper planning techniques, strategy, and FPGA tool flow to get up and designing an FPGA design now.
Essentials of FPGA Design
Duration: 1 Day
Course Date: 1 Mar | 1 Apr | 12 May | 1 Jun | 1 Jul | 18 Aug | 5 Sep | 3 Nov | 1 Dec
Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.
Designing for Performance
Duration: 2 Days
Course Date: 9-10 Mar | 4-5 Apr | 24-25 May | 8-9 Jun | 5-6 Jul | 4-5 Aug | 6-7 Sep | 4-5 Oct
Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.
Advanced FPGA Implementation
Duration: 2 Days
Course Date: 17-18 Mar | 6-7 Apr | 26-27 May | 13-14 Jul | 8-9 Aug | 8-9 Sep | 6-7 Oct | 7-8 Dec
Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE® 11.3 design suite and Xilinx hardware. Seven labs provide hands-on experience in this two-day course and cover the Xilinx Synthesis Technology (XST) tools.
Designing with PlanAhead Analysis and Design Tool
Duration: 2 Days
Course Date: 14-15 Jun | 24-25 Aug | 9-10 Nov
Learn to increase design performance and achieve repeatable results by using the PlanAhead® software tool. Topics include: a product overview, synthesis and project tips, design analysis, creating a floorplan, improving performance, experimenting with implementation options, incremental methodology, block-based IP design, and I/O pin assignment.
Designing with the Virtex-5 Family
Duration: 2 Days
Course Date: 14-15 Apr | 22-23 Jun | 13-14 Dec
Interested in learning how to effectively utilize Virtex®-5 FPGA architectural resources? Targeted towards experienced Xilinx users who have already completed Essentials of FPGA Design and Designing for Performance, this course focuses on understanding as well as designing into several of the resources found in this popular device.
Designing with the Virtex-6 Family
Duration: 2 Days
Course Date: 19-20 Apr | 28-29 Jun | 21-22 Sep | 15-16 Nov
Are you interested in learning how to effectively utilize Virtex®-6 FPGA architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in these popular device families.
Designing with the Spartan-6 Family
Duration: 2 Days
Course Date: 21-22 Apr | 25-26 Jul | 28-29 Sep | 21-22 Dec
Are you interested in learning how to effectively utilize Spartan®-6 FPGA architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in these popular device families.
Designing with the Spartan-6 and Virtex-6 Families
Duration: 3 Days
Course Date: 23-25 Mar | 11-13 Oct
Are you interested in learning how to effectively utilize Spartan®-6 or Virtex®-6 FPGA architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in these popular device families.
Design Techniques for Lower Cost
* Available Upon Request
This course will appeal to engineers who have an interest in developing low-cost products, particularly in high-volume markets. The course and exercises cover several different design techniques, which will be interesting and challenging for any digital designer regardless of the final application.
Xilinx Partial Reconfiguration Tools & Techniques NEW
* Available Upon Request
This course demonstrates how to use the ISE, PlanAhead, and Embedded Development Kit (EDK) software tools to construct, implement, and download a Partially Reconfigurable (PR) FPGA design. You will gain a firm understanding of PR technology and learn how successful PR designs are completed. You will also identify best design practices and understand the subtleties of the PR design flow.
Designing for Performance for CPLDs
* Available upon request
Designing for Performance for CPLDs is an intermediate-level course that provides a comprehensive overview of the CPLD software flow. By applying the techniques presented in this course, you will be able to enhance design performance and make the best possible use of Xilinx CPLD architectures.
Fundamentals of CPLD Design
* Available upon request
This comprehensive course provides you with an introduction to designing with Xilinx CPLDs by using the ISE® series software tools. You will learn the basics of ISE software flow and how to interpret CPLD reports for optimum performance designs.
Designing with Ethernet MAC Controllers
* Available upon request
Become acquainted with the various solutions that Xilinx offers for Ethernet connectivity. Learn the basics of the Ethernet standard, protocol, and OSI model while applying Xilinx solutions via hands-on laboratory exercises. Perform simulation to understand fundamental principles and obtain the knowledge to assess hardware design considerations and software development requirements.
Designing with Multi-Gigabit Serial I/O
* Available upon request
Learn how to employ RocketIO® GTP and GTX serial transceivers in your Virtex®-5 LXT, SXT, FXT, or TXT FPGA design. Understand and utilize the features of the RocketIO transceiver blocks, such as CRC, 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the Architecture Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.
Designing a LogiCORE PCI Express System
* Available upon request
Attending the Designing a LogiCORE PCI Express System will provide you a working knowledge of how to implement a Xilinx PCI Express® core in your applications. This course focuses on the implementation of a Xilinx PCI Express system with supporting logic and example designs. With this experience, you can improve your time to market with your PCIe core design. Various Xilinx PCI Express core products will be enumerated to aid you in selecting the proper solution. This course focuses on the Virtex®-5 FPGA PCIe Endpoint Block Plus and the Spartan®-3 PCIe integrated Endpoint PIPE block.
DSP Design Using System Generator
* Available upon request
This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification using the Xilinx FPGA capabilities.
Essential DSP Implementation Techniques for Xilinx FPGAs NEW
* Available upon request
This course provides a foundation for Digital Signal Processing (DSP) techniques for Xilinx FPGAs. The course begins with a refresher of basic binary number theory, mathematics, and the essential features within the FPGA that are important to signal processing. The body of the course explores a variety of filter techniques with emphasis on optimal implementation in Xilinx devices and continues with an examination of FFTs, video, and image processing.
Designing with Verilog
Duration: 3 Days
Course Date: 29-31 Mac | 18-20 May | 19-21 Jul | 16-18 Aug | 19-21 Oct | 27-29 Dec
This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001.
Designing with VHDL
Duration: 3 Days
Course Date: 27-29 Jul | 23-25 Nov
This comprehensive course is a thorough introduction to the VHDL language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course.
Embedded Systems Development
* Available upon request
Xilinx FPGAs provide a new level of system design capabilities through soft MicroBlaze® processors, hard PowerPC® processors, and silicon-efficient architectural resources. This course brings experienced FPGA designers up to speed on developing embedded systems using the Embedded Development Kit (EDK). The features and capabilities of the Xilinx MicroBlaze soft processor and the PowerPC 440 processor are also included in the lectures and labs. The hands-on labs provide experience with the development, debugging, and simulation of an embedded system.
Advanced Features and Techniques of Embedded Systems Development
* Available upon request
Advanced Features and Techniques of Embedded Systems Development provides embedded systems developers the necessary skills to develop complex embedded systems and enables them to improve their designs by using the tools available in the Embedded Development Kit (EDK). This course also helps developers understand and utilize advanced components of embedded systems design for architecting a complex system.
Embedded Open-Source Linux Development
* Available upon request
This intermediate-level, two-day course provides embedded systems developers with experience in creating an embedded open-source Linux operating system on a Xilinx development board. The course offers students hands-on experience from building the environment to booting the system using a basic, single-processor System on Chip (SoC) design with Linux 2.6 from the Xilinx kernel tree.
