Service Offerings

Symmid is also a full service provider of mixed signal design technology. Symmid offerings range from a complete SOC implementation, custom circuit design, IP blocks, layout services and sign-off audits.

Mixed signal circuit design are becoming a major bottleneck in the SoC design cycle. The process of designing analog circuits is perhaps closer to be an art and requires good intuition, compared to the digital design process which is very well structured. Symmid is committed to provide to its customers the most comprehensive mixed signal design services using its local design team, and its extensive network of design partners. Our design team can handle any special needs ranging from specialized IP blocks, filters, PLLs, power supplies, OPAMPS, complete transceiver solutions, I/O blocks, and more. The following are the highlights of our offerings:

• Specification developments and market requirements documentations.
• System design, architecture, partitioning, and performance verifications.
• Identification of building blocks.
• Technology and foundry selection- development PDKs and libraries.
• High level behavioral modeling (MATLAB, and VHDL/Verilog AMS).
• Schematic entry.
• Simulation support: device level, behavioral levels, noise analysis, statistical analysis, and circuit optimization.
• Circuit layout, floor planning and routing.
• Custom and schematic driven layout.
• Post layout simulation.
• Custom and schematic driven layout.
• Physical verifications: DRC, LVS, ERC, DSM extraction (2.5 and 3 D), and antenna verification.
• Analog circuit optimization.
• Substrate coupling analysis.
• Statistical and corner analysis.
• Test Program Development.
• Custom block level design.
• Specialized I/O blocks.
• EDA and methodology consulting.

Symmid is fully committed to deliver the most comprehensive ASIC/ASSP/FPGA design services to meet customers' needs (cost, time, quality). Our customers can enjoy our flexible engagement models: Turnkey, Partial, or Collaborative design. Services can be performed on customer's site or on our premises. The services we offer include but not limited to the following:

System Level

• Development of the market requirements documentations.
• Specification developments.
• System design, architecture exploration, partitioning, and performance verifications.
• Technology and foundry selection.
• System-level algorithm design using MATLAB, C, C++, SPW, and more.
• High-level RTL Design using VHDL, Verilog, VERILOG/VHDL AMS.
• Behavioral and RTL models development (block level).
• Test bench development and design verification.
• HW/SW Co-Design & Co-Verification.
• System Emulation and acceleration.
• EDA and methodology consulting.

Chip (RTL) Level

• Frontend logic design.
• Logic Synthesis.
• FPGA to ASIC design conversion service.
• Test bench development and design verification.
• Design-for-Test (Scan, JTAG and BIST).
• ATPG and Test Program Development.
• Design Verification (formal & test bench).
• Chip level emulation and acceleration.
• Power analysis and optimization (pre/post-layout).
• Backend layout design and floor planning.
• Physical implementation (P&R) and timing closure.
• Physical optimization from RTL or netlist handoff.
• Clock-Tree synthesis and balancing and post clock tree refinement.
• Physical verifications: DRC, LVS, ERC, DSM extraction (2.5 and 3 D), and antenna verification.
• Static Timing Analysis (STA).
• Formal verification (RTL2gate & gate2gate).
• Signal Integrity (SI) checks.